> On 18 March 2015 at 06:23, MyungJoo Ham <myungjoo....@samsung.com> wrote:
> >> As the DT bindings don't have an operating-points property any more,
> >> build the OPP table from the frequencies supported by the EMC clock.
> >>
> >> Signed-off-by: Tomeu Vizoso <tomeu.viz...@collabora.com>
> >> ---
[]
> >>
> >> + for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
> >> + rate = clk_round_rate(tegra->emc_clock, rate);
> >> + dev_pm_opp_add(&pdev->dev, rate, 0);
> >> + }
> >> +
> >
> > Although I am not going to NACK for the single-time performance of a
> > single device driver for a device that I do not have or fully understand,
> > please note that you may be wasting several billion cycles unless
> > your product is running at MHZ/kHZ level.
> >
> > What is going on with this loop? Do you really have such a
> > virtually-continuous
> > frequency scaling in your product? (Wow.... but in such a case, I don't
> > think
> > OPP is appropriate.)
>
> Actually, that loop is expected to only execute as many times as
> frequencies are supported by the clock. This is using knowledge of the
> clock always rounding up when possible, which I think is fine in this
> case.
Ah. ok. you are using "clk_frac_div_round_rate" of
drivers/clk/tegra/clk-divider.c (DIV_ROUND_UP)
Great. Thanks for the clarification.
Cheers,
MyungJoo
>
> Regards,
>
> Tomeu
>
