> OK, I guess when I get some time, I'll start testing all the i386 bitop > functions, comparing the asm with the gcc versions. Now could someone > explain to me what's wrong with testing hot cache code. Can one > instruction retrieve from memory better than others?
To add one to Linus' list, note that all current AMD & Intel chips record instruction boundaries in L1 cache, either predecoding on L1 cache load, or marking the boundaries on first execution. The P4 takes it to an extreme, but P3 and K7/K8 do it too. The result is that there are additional instruction decode limits that apply to cold-cache code. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
