On 5/1/2015 2:18 AM, Ingo Molnar wrote:
* Aravind Gopalakrishnan <aravind.gopalakrish...@amd.com> wrote:
Newer AMD processors can generate deferred errors and can be configured
to generate APIC interrupts on such events.
What's the wider context of this? What is it good for?
I suspect it's MCE related, but only from the diffstat:
Deferred errors indicate error conditions that were not corrected, but
require no action from S/W (or action is optional).
These errors provide info about a latent UC MCE that can occur when a
poisoned data is consumed by the processor.
HTH,
I shall include the short description in the cover letter of V2.
Thanks,
-Aravind.
arch/x86/kernel/cpu/mcheck/mce.c | 1 +
arch/x86/kernel/cpu/mcheck/mce_amd.c | 105 ++++++++++++++++++++++++++++++-
Please provide proper high level description for the changes.
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