On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote:
> The A80 includes an ARM CCI-400 interconnect to support multi-cluster
> CPU caches.
>
> Also add the default clock frequency for the CPUs.
>
> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
> ---
> arch/arm/boot/dts/sun9i-a80.dtsi | 46
> ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi
> b/arch/arm/boot/dts/sun9i-a80.dtsi
> index ca272e92b85d..200e712fbf0e 100644
> --- a/arch/arm/boot/dts/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
> @@ -58,48 +58,64 @@
> cpu0: cpu@0 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x0>;
> };
>
> cpu1: cpu@1 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x1>;
> };
>
> cpu2: cpu@2 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x2>;
> };
>
> cpu3: cpu@3 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x3>;
> };
>
> cpu4: cpu@100 {
> compatible = "arm,cortex-a15";
> device_type = "cpu";
> + cci-control-port = <&cci_control1>;
> + clock-frequency = <9000000>;Isn't the clock frequency property is supposed to be the maximum frequency of that CPU in Linux? It looks odd that the A15 are clocked at a lower frequency than the A7... Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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