2015-05-21 18:21+0200, Paolo Bonzini:
> On 21/05/2015 18:20, Radim Krčmář wrote:
> > 
> >> > +        set_desc_base(&desc,      get_smstate(u32, smbase, offset + 8));
> >> > +        set_desc_limit(&desc,     get_smstate(u32, smbase, offset + 4));
> >> > +        rsm_set_desc_flags(&desc, get_smstate(u32, smbase, offset));
> > (There wan't a layout where this would be right, so we could save the
> >  shifting of those flags in 64 bit mode.  Intel P6 was close, and they
> >  had only 2 bytes for access right, which means they weren't shifted.)
> 
> Check the AMD architecture manual.

I must be blind, is there more than Table 10-2?

(And according to ADM manual, we are overwriting GDT and IDT base at
 offset 0xff88 and 0xff94 with ES and CS data, so it's not the best
 reference for this case ...)
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