On Tue, Jun 09, 2015 at 07:06:14PM +0200, Borislav Petkov wrote: > On Tue, Jun 09, 2015 at 09:44:59AM -0700, Andy Lutomirski wrote: > > [1] For those who weren't bitten by this repeatedly, modern Intel CPUs > > (at least Sandy Bridge, anyway) will, by default, detect when all > > cores are in C1 or deeper, think to themselves "wow, the OS selected > > C1 -- it must want a very deep sleep indeed", and put the whole > > package into some kind of deep sleep state. The subsequent wakeup > > takes tens of milliseconds. Doing this in udelay would be awful. > > That's a good point. Reportedly, the current MWAITX enters something > between C0 and C1 but the way I understood it, going forward, it will > enter deeper sleep states. > > So for shallow C-states, your idle enter/exit latency is low enough but > I'd guess deeper states would be a problem. >
Andy, Boris, that's right. Thanks. :) If MWAITX will enter C1 and restore back repeatedly. It will impact the accuracy of delay. I will ask HW designer to check if it already has configuration to control the target power state. Thanks, Rui -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
