On Tue, Jun 09, 2015 at 02:54:01PM -0700, Linus Torvalds wrote: > On Tue, Jun 9, 2015 at 2:14 PM, Dave Hansen <dave.han...@intel.com> wrote: > > > > The 0 cycle TLB miss was also interesting. It goes back up to something > > reasonable if I put the mb()/mfence's back. > > So I've said it before, and I'll say it again: Intel does really well > on TLB fills.
Assuming the page tables are cache-hot... And hot here does not mean L3 cache, but higher. But a memory intensive workload can easily violate that. That's why I'm dubious of all these micro benchmarks. They won't be clearing caches. They generate unrealistic conditions in the CPU pipeline and overestimate the cost of the flushes. The only good way to measure TLB costs is macro benchmarks. -Andi -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
