* kan.li...@intel.com <kan.li...@intel.com> wrote:
> From: Kan Liang <kan.li...@intel.com>
>
> This patchkit intends to support Intel core misc PMUs. There are
> miscellaneous
> free running (read-only) counters in core. Some new PMUs called core misc
> PMUs
> are composed to include these counters. The counters include TSC, IA32_APERF,
> IA32_MPERF, IA32_PPERF, SMI_COUNT, CORE_C*_RESIDENCY and PKG_C*_RESIDENCY.
> There
> could be more in future platform.
Could you please do something like:
s/perf_event_intel_core_misc.c/perf_event_x86/
and in general propagate it to a core perf x86 position?
This feature is not Intel specific per se, although the initial MSRs you are
supporting are Intel specific (and that is fine).
Thanks,
Ingo
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
