Hi all, while trying to get the devicetree overlays working using Alan's simple-fpga-bus I couldn't find a way to independently reset parts of the PL logic. I might have missed something and this exists already somewhere, in that case, oh well ...
If Sören or Michael could take a look at this to let me know if this is fundamentally wrong, that would be great. Thanks, Moritz Moritz Fischer (3): docs: dts: Added documentation for Xilinx Zynq PL Reset bindings. dts: zynq: Add devicetree entry for PL reset controller. reset: reset-zynq-pl: Adding support for Xilinx Zynq PL reset. .../devicetree/bindings/reset/zynq-reset-pl.txt | 13 ++ arch/arm/boot/dts/zynq-7000.dtsi | 6 + drivers/reset/Makefile | 1 + drivers/reset/reset-zynq-pl.c | 142 +++++++++++++++++++++ 4 files changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset-pl.txt create mode 100644 drivers/reset/reset-zynq-pl.c -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
