On Tue, Jun 30, 2015 at 04:24:27PM +0530, Laxman Dewangan wrote: > Tegra I2C controller required to configure the clock divisor > register inside controller to different value based on the clock > speed. The recommended clock divisor for the I2C controller for > standard/fast mode is 0x19 and for fast-mode plus is 0x10. > > Add support to configure clock divisor register of I2C controller > based on bus clock rate. > > This clock divisor is supported form T114 onwards. > > This is based on change done by > Chaitanya Bandi <ban...@nvidia.com> > > Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> > Signed-off-by: Chaitanya Bandi <ban...@nvidia.com>
Applied to for-next, thanks!
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