This patch introduces an algorithm that computes the average power by
reading a delta value of “core power accumulator” register during
measurement interval, and then dividing delta value by the length of
the time interval.
User is able to use power1_acc entry to measure the processor power
consumption and power1_acc just needs to be read twice with an needed
interval in-between.
A simple example:
$ cat /sys/bus/pci/devices/0000\:00\:18.4/hwmon/hwmon0/power1_acc
$ sleep 10000s
$ cat /sys/bus/pci/devices/0000\:00\:18.4/hwmon/hwmon0/power1_acc
The result is current average processor power consumption in 10000
seconds. The unit of the result is uWatt.
Signed-off-by: Huang Rui <ray.hu...@amd.com>
---
drivers/hwmon/fam15h_power.c | 62 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
index d529e4b..3bab797 100644
--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
@@ -60,6 +60,7 @@ struct fam15h_power_data {
u64 cu_acc_power[MAX_CUS];
/* performance timestamp counter */
u64 cpu_sw_pwr_ptsc[MAX_CUS];
+ struct mutex acc_pwr_mutex;
};
static ssize_t show_power(struct device *dev,
@@ -121,17 +122,74 @@ static DEVICE_ATTR(power1_crit, S_IRUGO, show_power_crit,
NULL);
static struct attribute_group fam15h_power_group;
__ATTRIBUTE_GROUPS(fam15h_power);
+static ssize_t show_power_acc(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int cpu, cu, cu_num, cores_per_cu;
+ u64 curr_cu_acc_power[MAX_CUS],
+ curr_ptsc[MAX_CUS], jdelta[MAX_CUS];
+ u64 tdelta, avg_acc;
+ struct fam15h_power_data *data = dev_get_drvdata(dev);
+
+ cores_per_cu = amd_get_cores_per_cu();
+ cu_num = boot_cpu_data.x86_max_cores / cores_per_cu;
+
+ for (cpu = 0, avg_acc = 0; cpu < cu_num * cores_per_cu; cpu +=
cores_per_cu) {
+ cu = cpu / cores_per_cu;
+ if (rdmsrl_safe_on_cpu(cpu, MSR_F15H_PTSC, &curr_ptsc[cu])) {
+ pr_err("Failed to read PTSC counter MSR on core%d\n",
+ cpu);
+ return 0;
+ }
+
+ if (rdmsrl_safe_on_cpu(cpu, MSR_F15H_CU_PWR_ACCUMULATOR,
+ &curr_cu_acc_power[cu])) {
+ pr_err("Failed to read compute unit power accumulator
MSR on core%d\n",
+ cpu);
+ return 0;
+ }
+
+ if (curr_cu_acc_power[cu] < data->cu_acc_power[cu]) {
+ jdelta[cu] = data->max_cu_acc_power +
curr_cu_acc_power[cu];
+ jdelta[cu] -= data->cu_acc_power[cu];
+ } else {
+ jdelta[cu] = curr_cu_acc_power[cu] -
data->cu_acc_power[cu];
+ }
+ tdelta = curr_ptsc[cu] - data->cpu_sw_pwr_ptsc[cu];
+ jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
+ do_div(jdelta[cu], tdelta);
+
+ mutex_lock(&data->acc_pwr_mutex);
+ data->cu_acc_power[cu] = curr_cu_acc_power[cu];
+ data->cpu_sw_pwr_ptsc[cu] = curr_ptsc[cu];
+ mutex_unlock(&data->acc_pwr_mutex);
+
+ /* the unit is microWatt */
+ avg_acc += jdelta[cu];
+ }
+
+ return sprintf(buf, "%u\n", (unsigned int) avg_acc);
+}
+static DEVICE_ATTR(power1_acc, S_IRUGO, show_power_acc, NULL);
+
static int fam15h_power_init_attrs(struct pci_dev *pdev)
{
int n = FAM15H_MIN_POWER_GROUPS;
struct attribute **fam15h_power_attrs;
struct cpuinfo_x86 *c = &boot_cpu_data;
+ u32 cpuid;
if (c->x86 == 0x15 &&
((c->x86_model <= 0xf) ||
(c->x86_model >= 0x60 && c->x86_model <= 0x6f)))
n += 1;
+ cpuid = cpuid_edx(0x80000007);
+
+ /* check if processor supports accumulated power */
+ if (cpuid & BIT(12))
+ n += 1;
+
fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
sizeof(*fam15h_power_attrs),
GFP_KERNEL);
@@ -148,6 +206,9 @@ static int fam15h_power_init_attrs(struct pci_dev *pdev)
(c->x86_model >= 0x60 && c->x86_model <= 0x6f)))
fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
+ if (cpuid & BIT(12))
+ fam15h_power_attrs[n++] = &dev_attr_power1_acc.attr;
+
fam15h_power_group.attrs = fam15h_power_attrs;
return 0;
@@ -311,6 +372,7 @@ static int fam15h_power_probe(struct pci_dev *pdev,
if (ret)
return ret;
+ mutex_init(&data->acc_pwr_mutex);
data->pdev = pdev;
hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
--
1.9.1
--
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