Em Mon, Aug 31, 2015 at 04:58:40PM +0300, Adrian Hunter escreveu: > The MPX instructions are presently not described in the SDM > opcode maps, and there are not encoding characters for bnd > registers, address method or operand type. So the kernel > opcode map is using 'Gv' for bnd registers and 'Ev' for > everything else. That is fine because the instruction > decoder does not use that information anyway, except as > an indication that there is a ModR/M byte. > > Nevertheless, in some cases the 'Gv' and 'Ev' are the wrong > way around, BNDLDX and BNDSTX have 2 operands not 3, and it > wouldn't hurt to identify the mandatory prefixes. > > This has no effect on the decoding of valid instructions, > but the addition of the mandatory prefixes will cause some > invalid instructions to error out that wouldn't have > previously. > > Note that perf tools has a copy of the instruction decoder > and provides a test for new instructions which includes MPX > instructions e.g. > > $ perf test list 2>&1 | grep "x86 ins" > 39: Test x86 instruction decoder - new instructions > $ perf test 39 > 39: Test x86 instruction decoder - new instructions : Ok > > Or to see the details: > > $ perf test -v 39
this is a handy shortcut, but I think that sometimes showing that one can also do it using the test description is handy, i.e. I forgot the number of it was reordered, doing it like: [root@zoo linux]# perf test syscall 2: detect openat syscall event : Ok 3: detect openat syscall event on all cpus : Ok 14: Generate and check syscalls:sys_enter_openat event fields: Ok [root@zoo linux]# Also works, which, for your case would be 'perf test x86', oops, that would also catch: [root@zoo linux]# perf test x86 6: x86 rdpmc test : Ok [root@zoo linux]# :-) - Arnaldo > Signed-off-by: Adrian Hunter <adrian.hun...@intel.com> > --- > arch/x86/lib/x86-opcode-map.txt | 8 ++++++-- > tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 8 ++++++-- > 2 files changed, 12 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt > index 816488c0b97e..a02a195d219c 100644 > --- a/arch/x86/lib/x86-opcode-map.txt > +++ b/arch/x86/lib/x86-opcode-map.txt > @@ -353,8 +353,12 @@ AVXcode: 1 > 17: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1) > 18: Grp16 (1A) > 19: > -1a: BNDCL Ev,Gv | BNDCU Ev,Gv | BNDMOV Gv,Ev | BNDLDX Gv,Ev,Gv > -1b: BNDCN Ev,Gv | BNDMOV Ev,Gv | BNDMK Gv,Ev | BNDSTX Ev,GV,Gv > +# Intel SDM opcode map does not list MPX instructions. For now using Gv for > +# bnd registers and Ev for everything else is OK because the instruction > +# decoder does not use the information except as an indication that there is > +# a ModR/M byte. > +1a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev > +1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv > 1c: > 1d: > 1e: > diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt > b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt > index 816488c0b97e..a02a195d219c 100644 > --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt > +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt > @@ -353,8 +353,12 @@ AVXcode: 1 > 17: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1) > 18: Grp16 (1A) > 19: > -1a: BNDCL Ev,Gv | BNDCU Ev,Gv | BNDMOV Gv,Ev | BNDLDX Gv,Ev,Gv > -1b: BNDCN Ev,Gv | BNDMOV Ev,Gv | BNDMK Gv,Ev | BNDSTX Ev,GV,Gv > +# Intel SDM opcode map does not list MPX instructions. For now using Gv for > +# bnd registers and Ev for everything else is OK because the instruction > +# decoder does not use the information except as an indication that there is > +# a ModR/M byte. > +1a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev > +1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv > 1c: > 1d: > 1e: > -- > 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
