On Tue, Sep 15, 2015 at 12:55:15PM +0300, Mikko Perttunen wrote: > The new determine_rate prototype allows for clock rates exceeding > 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate > instead of round_rate and unlock the top rates supported by the > Tegra124. > > Signed-off-by: Mikko Perttunen <mikko.perttu...@kapsi.fi> > --- > drivers/clk/tegra/clk-dfll.c | 15 ++++++++------- > drivers/clk/tegra/cvb.c | 7 ------- > 2 files changed, 8 insertions(+), 14 deletions(-)
I've applied this to the for-4.4/clk branch in the Tegra tree. Thanks, Thierry
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