On Fri, Oct 01, 1999 at 08:14:53PM -0700, Dave Shepperd wrote:
> > affected by this problem. The sole exception is the RM7000 which has
> > (cache-size / 4kb)-way, that is 8-way associative caches which completly
> > elleminate all pathological sympthoms of virtual indexed caches.
>
> You are correct that the RM7000 won't suffer the problem, but it is because it
> uses physical indexing instead of virtual indexing. FYI the RM7000 has 4-way
> set associativity on both the primary and secondary caches.
It definately uses virtual indexing like about every modern CPU. The
reason is simple - the physical address is available only much later
after the TLB lookup has completed.
You're right about 4-way associativity - I was remembering it'd have 32kb
per primary cache but they're only 16kb each which as per my formula
from above results in 4-way caches necessary.
So in effect only bits 5 to 11 are used to index the cache - and those
don't get changed by the address translation process.
Ralf
