On Saturday 07 December 2013, dingu...@altera.com wrote:
> -static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
> -{
> - /*
> - * Exynos4412 and Exynos5250 extends the use of CMD register with the
> - * use of bit 29 (which is reserved on standard MSHC controllers) for
> - * optionally bypassing the HOLD register for command and data. The
> - * HOLD register should be bypassed in case there is no phase shift
> - * applied on CMD/DATA that is sent to the card.
> - */
> - if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
> - *cmdr |= SDMMC_CMD_USE_HOLD_REG;
> -}
Hmm, according to the comment that gets deleted here, it seems that older
versions of this controller don't support that function, right?
If that's true, we may have to also check the version of the MSHC before
setting this.
Arnd
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