Am Samstag, 7. Dezember 2013, 04:20:22 schrieb dingu...@altera.com: > From: Dinh Nguyen <dingu...@altera.com> > > This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is > operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200. > > According to the Synopsys databook :"To meet the relatively high Input Hold > Time requirement for SDR12, SDR25, and other MMC speed modes, you should > program bit[29]use_hold_Reg of the CMD register to 1'b1;"..."However, for > the higher speed modes of SDR104, SDR50 and DDR50, you can meet the much > smaller Input Hold Time requirement of 0.8ns by bypassing the Hold Register > (Path A in Figure 10-8, programming CMD.use_hold_reg = 1'b0) and then > adding delay elements on the output path as indicated. > > Also, "Never set CMD.use_hold_reg = 1 and cclk_in_drv phase shift to 0 at > the same time. This would add an extra one-cycle delay on the output path, > resulting in incorrect behavior." > > This information is taking from the v2.50a of the Synopsys Designware Cores > Mobile Storage Host Databook. > > Signed-off-by: Dinh Nguyen <dingu...@altera.com> > ---
Acked-by: Heiko Stuebner <he...@sntech.de> on a rockchip,rk3066 (dw_mmc 10214000.dwmmc: Version ID is 240a) Tested-by: Heiko Stuebner <he...@sntech.de> -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
