On Wed, 13 Oct 1999, Alan Cox wrote: > > A number of newer chips have Rx interrupt mitigation/coalescence e.g. the > > Hamachi, Starfire and 21143-TD. Presumably the new Intel chips have > > something undocumented (based on nebulous marketing claims). > > If the Intel chip is I2O they will have. Of course the intel board being > I2O is probably something thats too bright an idea for chipzilla. I don't see an overwhelming advantage for I2O. I hear all of the claims, and most sound like one trick ponies e.g. networks cards that will do no-CPU-intervention bridging. > > On related topices, the chip should also > > - measure the interrupt latency, > > Why is this of interest ? Internally the chip can estimate how early to raise an interrupt to minimize the latency. The 3Com chips have a time-since-interrupt-raised register, intended for calculating the value for the early-Rx interrupt. I've used it for getting latency histograms, but it's too much overhead for normal driver operation. (Taking two interrupts per Rx packet to minimize latency isn't a good trade-off.) > > triggering underruns. > > - Have variable Rx DMA thresholds, starting the Rx DMA early (predicting a > > minimum-sized packet) when the Rx pipeline is empty. > > Or overlapping DMA's. Even in MCA bus days the 3c527 got amazing performance > for its time because it fed one packet to the chip fifo as it pulled the > next into the on card buffer space. Most modern chips have 2KB on-chip FIFOs and interleave Rx and Tx DMA operation. Donald Becker [EMAIL PROTECTED] USRA-CESDIS, Center of Excellence in Space Data and Information Sciences. Code 930.5, Goddard Space Flight Center, Greenbelt, MD. 20771 301-286-0882 http://cesdis.gsfc.nasa.gov/people/becker/whoiam.html - To unsubscribe from this list: send the line "unsubscribe linux-net" in the body of a message to [EMAIL PROTECTED]
