Hi, The three patches you sent (fix CONFIG_OMAP_RESET_CLOCKS, fix dss1_alwon_clk and this one) seem to fix problems I was seeing with retention.
-Tero >-----Original Message----- >From: ext Paul Walmsley [mailto:[EMAIL PROTECTED] >Sent: 25 September, 2008 17:39 >To: linux-omap@vger.kernel.org >Cc: Kristo Tero (Nokia-D/Tampere); [EMAIL PROTECTED] >Subject: [PATCH] OMAP3 clock: put DPLL into bypass if bypass >rate = clk->rate, not hardware rate > > >When a non-CORE DPLL is enabled via >omap3_noncore_dpll_enable(), use the user's desired rate in >clk->rate to determine whether to put the DPLL into bypass or >lock mode, rather than reading the DPLL's current idle state >from its hardware registers. > >This fixes a bug observed when leaving retention. Non-CORE >DPLLs were not being relocked when downstream clocks >re-enabled; rather, the DPLL entered bypass mode. > >Problem reported by Tero Kristo <[EMAIL PROTECTED]>. > >Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> >--- > arch/arm/mach-omap2/clock34xx.c | 4 +--- > 1 files changed, 1 insertions(+), 3 deletions(-) > >diff --git a/arch/arm/mach-omap2/clock34xx.c >b/arch/arm/mach-omap2/clock34xx.c index c89d6bc..df258f7 100644 >--- a/arch/arm/mach-omap2/clock34xx.c >+++ b/arch/arm/mach-omap2/clock34xx.c >@@ -281,9 +281,7 @@ static int >omap3_noncore_dpll_enable(struct clk *clk) > if (!dd) > return -EINVAL; > >- rate = omap2_get_dpll_rate(clk); >- >- if (dd->bypass_clk->rate == rate) >+ if (clk->rate == dd->bypass_clk->rate) > r = _omap3_noncore_dpll_bypass(clk); > else > r = _omap3_noncore_dpll_lock(clk); > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
