Santosh <santosh.shilim...@ti.com> writes:
> On Tuesday 13 September 2011 02:36 AM, Kevin Hilman wrote:
>> Santosh Shilimkar<santosh.shilim...@ti.com> writes:
>>
>>> This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
>>> retention (CSWR) is not supported by hardware design.
>>>
>>> The CPUx OFF mode isn't supported on OMAP4430 ES1.0
>>>
>>> CPUx sleep code is common for hotplug, suspend and CPUilde.
>>>
>>> Signed-off-by: Santosh Shilimkar<santosh.shilim...@ti.com>
>>> Cc: Kevin Hilman<khil...@ti.com>
>>
>> [...]
>>
>>> @@ -38,6 +39,11 @@ void __iomem *omap4_get_scu_base(void)
>>>
>>> void __cpuinit platform_secondary_init(unsigned int cpu)
>>> {
>>> + /* Enable NS access to SMP bit for this CPU on EMU/HS devices */
>>> + if (cpu_is_omap443x()&& (omap_type() != OMAP2_DEVICE_TYPE_GP))
>>
>> A comment here about why this is 443x specific would be helpful.
>>
>> I see a comment in omap4_cpu_resume() that seems to indicate that SMP
>> bit is accessible on 446x NS devices, but repeating that commen here
>> would help future readability.
>>
> Ok. Will add comments here too. Was just trying to save some lines :)
heh, this is a negative side-effect of people caring primarily about
diffstat. :(
One other comment on this patch. You need spaces around the '&&' above.
Kevin
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