On Wed, 11 Nov 2009, Jason Gunthorpe wrote: | On Wed, Nov 11, 2009 at 05:44:59PM -0500, Richard Frank wrote: | | > Would anyone like to through out the list of HCAs that do this... I | > can guess at a few... and can ask the vendors directly.. if not.. . | > | > It would be much nicer to not hardcode names of adapters.. but that won't | > stop us.. :) | | Isn't it more complex than this? AFAIK the PCI-E standard does not | specify the order which data inside a single transfer becomes visible, | only how different transfers relate. To work on the most agressive | PCI-E system the HCA would have to transfer the last XX bytes as a | seperate PCI-E transaction without relaxed ordering.
I can't speak to the specifics of this on PCIe, but yes, by default the pcie transfers within a single tag can be unordered. | This is the sort of thing that might start to matter on QPI and HT | memory-interleaved configurations. A multi-cache line transfer will be | split up and completed on different chips - it may not be fully | coherent 100% of the time. HT is fine, by design, at least on AMD processors (probably don't care too much about the older sibyte cpus, since they weren't fully HT-compliant). I don't know about QPI. Dave Olson dave.ol...@qlogic.com -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
