From: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com> Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com> Signed-off-by: Simon Horman <horms+rene...@verge.net.au> --- arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index 0cd908796055..b4d679b04ad6 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -39,6 +39,16 @@ groups = "scif2_data"; function = "scif2"; }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; }; &scif2 { @@ -49,6 +59,9 @@ }; ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; renesas,ether-link-active-low; status = "okay"; -- 2.1.4