[PATCH 2/5] clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()

[Geert Uytterhoeven]

As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the Z clock on R-Car Gen2 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

This includes implementing range checking.

Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 drivers/clk/renesas/rcar-gen2-cpg.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c 
b/drivers/clk/renesas/rcar-gen2-cpg.c
index f596a2dafcf4d8d1..282266b32c51a36b 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -63,19 +63,22 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw 
*hw,
        return div_u64((u64)parent_rate * mult, 32);
 }
 
-static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *parent_rate)
+static int cpg_z_clk_determine_rate(struct clk_hw *hw,
+                                   struct clk_rate_request *req)
 {
-       unsigned long prate  = *parent_rate;
-       unsigned int mult;
+       unsigned long prate = req->best_parent_rate;
+       unsigned int min_mult, max_mult, mult;
 
-       if (!prate)
-               prate = 1;
+       min_mult = max(div_u64(req->min_rate * 32ULL, prate), 1ULL);
+       max_mult = min(div_u64(req->max_rate * 32ULL, prate), 32ULL);
+       if (max_mult < min_mult)
+               return -EINVAL;
 
-       mult = div_u64((u64)rate * 32, prate);
-       mult = clamp(mult, 1U, 32U);
+       mult = div_u64(req->rate * 32ULL, prate);
+       mult = clamp(mult, min_mult, max_mult);
 
-       return *parent_rate / 32 * mult;
+       req->rate = prate / 32 * mult;
+       return 0;
 }
 
 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -126,7 +129,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned 
long rate,
 
 static const struct clk_ops cpg_z_clk_ops = {
        .recalc_rate = cpg_z_clk_recalc_rate,
-       .round_rate = cpg_z_clk_round_rate,
+       .determine_rate = cpg_z_clk_determine_rate,
        .set_rate = cpg_z_clk_set_rate,
 };
 
-- 
2.17.1