On Thu, 14 Jan 1999, Jeffrey Mark Siskind wrote:
> Basically, I'm wondering:
>
> (a) if the bus gets saturated with four CPUs
you can saturate the bus easily by deliberately falling out of cache. I
dont know how a 440NX EDO performs, but an SDRAM based one does:
[root@moon xor]# ./xor_ben6
benchmark running as root, disabling irqs
CPU speed: 400.00 MHZ
onestream_store : 13004567 cycles. (209.96 MB/sec)
onestream_simple_load : 11584792 cycles. (235.69 MB/sec)
onestream_cached_load : 1716613 cycles. (1590.57 MB/sec)
as you can see, roughly 1.6G/sec is the bandwith towards the L1/L2 cache
subsystem.
> (b) how interleaved (440NX chipset) with 60ns EDO compares with noninterleaved
> (440BX chipset) with 100MHz SDRAM
a 440BX does:
[root@hell xor]# ./xor_ben6
benchmark running as root, disabling irqs
CPU speed: 300.00 MHZ
onestream_store : 11878919 cycles. (172.39 MB/sec)
onestream_simple_load : 7683543 cycles. (266.52 MB/sec)
onestream_cached_load : 1716653 cycles. (1192.90 MB/sec)
this has roughly the same main memory bandwith, since both are 100MHz.
(slightly better because i have bothered to download and read the 440BX
docs and have tweaked the memory controller to go faster that the BIOS
settings with setpci. setpci is cool!)
so the rule of thumb is: you can get a 5x bandwith and who knows how much
latency improvement if _not_ falling out of the cache. The Xeon clearly
wins in that case.
-- mingo
ps. here is the tweak script:
#
# tweak440bx: boosts the memory subsystem, if yours can take it.
# no guarantees. -- mingo
#
echo '- some SDRAM magic?'
setpci -s 0:0.0 77.b=00
echo '- fast page ready'
setpci -s 0:0.0 52.b=04
echo '- refresh up to 0.25 msec'
setpci -s 0:0.0 57.b=0d
echo '- CAS waitstates to 0'
setpci -s 0:0.0 58.b=00
echo '- CS#=3 doesnt work only for the most expensive SDRAM'
# setpci -s 0:0.0 76.b=1f
echo '- 4 open pages at once'
setpci -s 0:0.0 79.b=ff
echo '- infinite precharge timeout'
setpci -s 0:0.0 78.b=0f
echo '- no SDRAM powerdown'
setpci -s 0:0.0 7a.b=16
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