Has anybody measured memory bus bandwidth on a Quad Xeon? If you run four
simultaneous copies of your typical compute-bound jobs (that don't fit in L2
but OTOH don't have extremely high L2 miss rates) how does per-job speed
compare with a single copy running (and the three other CPUs idle or running
processes that fit totally in L2). How does it compare with the same job
running on a single or dual PII of the same clock speed and cache size on a
100MHz bus machine?
Basically, I'm wondering:
(a) if the bus gets saturated with four CPUs
(b) how interleaved (440NX chipset) with 60ns EDO compares with noninterleaved
(440BX chipset) with 100MHz SDRAM
Jeff (http://www.neci.nj.nec.com/homepages/qobi)
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