In message <[EMAIL PROTECTED]>,C S Hendrix writes:
>
> In message <[EMAIL PROTECTED]>, "Stephen C. Tweedie"
> wr
> ites:
>
> > Hi,
> >
> > On Wed, 2 Dec 1998 16:16:27 +0000 (GMT), [EMAIL PROTECTED]
> > (Alan Cox) said:
> >
> > > 32-64GB is out of the intel arena altogether. You are firmly in mainframe
> > > land unless clustering stuff would work. Go set Sun, IBM and SGI bidding
> > > against each other and get some third party disk quotes 8)
> >
> > Any particular reasons why? With 36-bit addressing and 3-level page
> > tables, there's no technical reason why Linux won't eventually be able
> > to address that much memory on Intel.
>
> Is there any OS that currently does this?
>
Yes,
Sequent's DYNIX/ptx does exactly this. With wide (64-bit) ptes, all 64GB of
physical address space can be addressed. Of course, your virtual address space
is still limited to 4GB per process, in the case of DYNIX/ptx, 3GB for user
and 1GB for the kernel. In large memory machines, 1GB of kernel virtual address
space is badly limiting so ptx has the ability to transparently unmap user
space and map in "extended kernel virtual address space" allowing 4GB of
KVA. This is done by playing interesting segment games. The performance
impact is surprisingly negligible. BTW, don't confuse this mode of operation
with the 4MB pages "extended addressing" mode in the PII that will apparently
be used by NT for some kind of buffer cache/ramdisk. The above fully supports
4K page addressability throughout the physical address range.
As you will gather from the above, the machine is not suited to working on
number-crunching problems with large data sets. However, it does make a
pretty impressive database server (see the TPC results).
> Do you know where in the Intel line 36-bit addressing started?
> I'm curious to know of my PPro can do this.
>
Yes it can. AFAIK, all PPROs can do this. Not sure if all PII's can. I seem
to recall addressing limitations on the "on-chip" L2 cache for the non-server
type PII chips. Xeon is not so limited.
The question here is, how much effort do you want to put into this. We have
it working because we have to. It is not at all "nice" to implement (the
combination of a speculating processor, playing games with segments,
re-writing four L1 ptes instead of one register, and having to handle NMIs
is an amazingly tricky problem). There may be more mileage in using the
"extended addressing" mode, or whatever it's called. If you want lots of
memory, then except in certain specialized cases (probably better handled
with Beowulf), you probably want lots of processors as well. In that case,
a great deal more work needs to be done on SMP scalability before playing
with the VM system to support the 32/36bit games on x86.
Tim
--
Tim Wright, Software Engineer, | Email: [EMAIL PROTECTED]
Sequent Computer Systems Inc., 15450, |
SW Koll Parkway, Beaverton, Oregon 97006 | Phone: +1-503-578-3822
"Law of Probability Dispersal: Whatever it is that hits the fan will not be
evenly distributed."
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