On Sun, 23 Apr 2000, Arnaldo Carvalho de Melo wrote:
> I was using 2.3.99-pre4-5 in a dual celeron ABIT BP6 mostly ok,
> mostly because from time to time I get this:
>
> APIC error interrupt on CPU#1, should never happen.
> ... APIC ESR0: 00000002
> ... APIC ESR1: 00000002
> ... bit 1: APIC Receive CS Error (hw problem).
>
> But aside from this the machine works ok, now with 2.3.99-pre6-5 the
> second CPU is not enabled and I get only one CPU working :(
Does it happen every time? Checksum errors indicate problems with the
inter-APIC bus. Normal interrupts get resent until succeeded in case of
such errors but INIT and StartUp inter-processor interrupts (IPIs) which
are used for waking up of secondary CPUs do not. They are only sent once
and if there is an error during the transmission they are simply ignored.
So if one of these IPIs gets lost, the relevant secondary CPU does not
boot.
Note that the BP6 problems are beaten to death every now and then and I
think I've seen some success reports after some BIOS upgrades, recently.
I don't have such a board and I'm not particularly interested in Abit
products but you might try to visit their web server and maybe search
mailing list archives for a definite solution. If after a BIOS upgrade
checksum errors disappear but the bootup problem remains, then I may look
into it, but there were only some timing changes in the secondary startup
code in pre6. I doubt they are the reason as they are more forgiving now
than they were before -- current timeout values actually match these
required by the Intel's MP specification.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: [EMAIL PROTECTED], PGP key available +
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