From: Thor Thayer <[email protected]> Altera's Arria10 SoC requires all write accesses of APB peripherals are 32-bit. The DesignWare documentation indicates this change is acceptable.
Request for Testing: Please test on legacy DesignWare SPI devices. If a problem is discovered, please reply to this thread. Additional Documentation To Support this Change: The DesignWare documentation DW_apb_ssi databook states: All registers in the DW_apb_ssi are addressed on 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect, reading from these bits returns 0. [1] Tested On: Altera CycloneV Development Kit Altera Arria10 Development Kit [1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a) Thor Thayer (1): spi: dw-spi: Convert 16bit accesses to 32bit accesses drivers/spi/spi-dw.c | 34 +++++++++++++++++----------------- drivers/spi/spi-dw.h | 10 ---------- 2 files changed, 17 insertions(+), 27 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
