From: Ma Haijun <mahaij...@gmail.com>
According to A10 user manual, the width of the drive configuration
for each pin is only 2 bits. Fix the mask so we don't touch values
for other pins.
Signed-off-by: Ma Haijun <mahaij...@gmail.com>
Signed-off-by: Chen-Yu Tsau <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/pinmux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c
b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 8428439..56671f6 100644
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -69,7 +69,7 @@ int sunxi_gpio_set_drv(u32 pin, u32 val)
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
drv = readl(&pio->drv[0] + index);
- drv &= ~(0xf << offset);
+ drv &= ~(0x3 << offset);
drv |= val << offset;
writel(drv, &pio->drv[0] + index);
--
1.8.5.2
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