GMAC requires a higher drive level for gigabit speeds.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/board.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 8c43ab6..6d555f0 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -156,8 +156,10 @@ int cpu_eth_init(bd_t *bis)
setbits_le32(&ccm->gmac_clk_cfg, (0x1 << 2) | (0x2 << 0));
/* Configure pin mux settings for GMAC */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
sunxi_gpio_set_cfgpin(pin, 5);
+ sunxi_gpio_set_drv(pin, 3);
+ }
designware_initialize(0, SUNXI_GMAC_BASE, 0x1,
PHY_INTERFACE_MODE_RGMII);
#endif
--
1.8.5.2
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