So that we can use it as a clocksource for modules, ie for mmc. This
allows discoupling the actual mmc clock rate we get from the ram speed,
and will lead to getting exact clockspeeds for mmc rather then something
approximately right.
As an added bonus this makes things easier on sun6i since pll5 cannot be
used as a module source at all there.
This has been tested on sun4i, sun5i and sun7i.
Signed-off-by: Hans de Goede <hdego...@redhat.com>
---
arch/arm/cpu/armv7/sunxi/clock.c | 18 +++++++++++-------
arch/arm/include/asm/arch-sunxi/clock-sun4i.h | 7 +------
arch/arm/include/asm/arch-sunxi/clock.h | 1 +
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index c4b19da..e3c8fef 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -33,17 +33,11 @@ static void clock_init_safe(void)
APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN5I
- /* Power on reset default for PLL6 is 2400 MHz, which is faster then
- * it can reliable do :| Set it to a 600 MHz instead. */
- writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
-#endif
#ifdef CONFIG_SUN7I
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
&ccm->ahb_gate0);
- writel(0x1 << PLL6_ENABLE_OFFSET | readl(&ccm->pll6_cfg),
- &ccm->pll6_cfg);
#endif
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}
#endif
@@ -101,6 +95,16 @@ unsigned int clock_get_pll5(void)
return 24000000 * n * k / p;
}
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = (rval >> 8) & 0x1f;
+ int k = ((rval >> 4) & 3) + 1;
+ return 24000000 * n * k / 2;
+}
+
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock-sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock-sun4i.h
index 68105d7..a85d541 100644
--- a/arch/arm/include/asm/arch-sunxi/clock-sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock-sun4i.h
@@ -117,12 +117,7 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0xa1005000
-#ifdef CONFIG_SUN5I
-#define PLL6_CFG_DEFAULT 0x21009911
-#endif
-#ifdef CONFIG_SUN7I
-#define PLL6_ENABLE_OFFSET 31
-#endif
+#define PLL6_CFG_DEFAULT 0xa1009911
#ifdef CONFIG_SUN5I
#define AHB_CLK_SRC_AXI 0
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index af301be..bfcc525 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -26,6 +26,7 @@ int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(int hz);
unsigned int clock_get_pll5(void);
+unsigned int clock_get_pll6(void);
#endif
#endif /* _SUNXI_CLOCK_H */
--
1.9.0
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