On 03/28/2014 01:45 PM, Hans de Goede wrote:
Hi,
On 03/28/2014 01:38 PM, Olliver Schinagl wrote:
On 03/28/2014 11:16 AM, Hans de Goede wrote:
Signed-off-by: Hans de Goede <hdego...@redhat.com>
---
arch/arm/cpu/armv7/sunxi/clock.c | 3 +++
arch/arm/include/asm/arch-sunxi/clock-sun6i.h | 21 +++++++++++++++++++++
drivers/mmc/sunxi_mmc.c | 9 ++++++++-
include/configs/sunxi-common.h | 2 --
4 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index e3c8fef..273aa3f 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -58,6 +58,9 @@ int clock_init(void)
/* open the clock for uart */
sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
+
+ /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
Shouldn't this only be done on sun6i then? as sun457i do have the SPL?
olliver
#else
And it is only done on sun6i, the #else above is where the non sun6i code
starts...
Ah, that bit got a little lost in translation then, probably a previous
patch. My dearest apologies!
Olliver
Regards,
Hans
/* uart clock source is apb1 */
sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
diff --git a/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
index 147e6c9..2f20d5d 100644
--- a/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
@@ -141,4 +141,25 @@ struct sunxi_ccm_reg {
#define APB2_FACTOR_M 0
#define APB2_FACTOR_N 0
+#define PLL6_CFG_DEFAULT 0x90041911
+
+#define AHB_GATE_OFFSET_MMC3 11
+#define AHB_GATE_OFFSET_MMC2 10
+#define AHB_GATE_OFFSET_MMC1 9
+#define AHB_GATE_OFFSET_MMC0 8
+#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+
+#define SUN6I_ABP1_RESET_BASE 0x01c202c0
+
+#define ABP1_RESET_OFFSET_MMC3 11
+#define ABP1_RESET_OFFSET_MMC2 10
+#define ABP1_RESET_OFFSET_MMC1 9
+#define ABP1_RESET_OFFSET_MMC0 8
+#define ABP1_RESET_OFFSET_MMC(n) (ABP1_RESET_OFFSET_MMC0 + (n))
+
#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4573621..4cb5dc7 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -77,7 +77,7 @@ struct sunxi_mmc_des {
u32 data_buf1_sz:13;
u32 data_buf2_sz:13;
u32 reserverd2_1:6;
-#elif defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#elif defined(CONFIG_SUN5I) || defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I)
#define SDXC_DES_NUM_SHIFT 16
#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
u32 data_buf1_sz:16;
@@ -203,6 +203,13 @@ static int mmc_clk_io_on(int sdc_no)
rval |= 1 << AHB_GATE_OFFSET_MMC(sdc_no);
writel(rval, &ccm->ahb_gate0);
+#if defined(CONFIG_SUN6I)
+ /* unassert reset */
+ rval = readl(SUN6I_ABP1_RESET_BASE);
+ rval |= 1 << ABP1_RESET_OFFSET_MMC(sdc_no);
+ writel(rval, SUN6I_ABP1_RESET_BASE);
+#endif
+
/* config mod clock */
pll_clk = clock_get_pll6();
/* should be close to 100 MHz but no more, so round up */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index dd7c668..212b621 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -81,7 +81,6 @@
/* mmc config */
/* Can't use MMC slot 0 if the UART is directed there */
-#ifndef CONFIG_SUN6I
#if !defined CONFIG_UART0_PORT_F || CONFIG_MMC_SUNXI_SLOT != 0
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
@@ -94,7 +93,6 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller
*/
#endif
-#endif
/* 4MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to linux-sunxi+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.
