On Tue, Sep 26, 2017 at 06:59:12AM +0000, Chen-Yu Tsai wrote: > Allwinner SoCs typically have two PLLs reserved for video related usage. > At the moment we only support using the first one to feed the HDMI > transmitter block's TMDS clock. > > Let the HDMI encoder's TMDS clock go through all of its parents when > calculating possible clock rates. This allows usage of the second video > PLL as its parent. > > Note that this does not handle conflicting pixel clocks. It is entirely > possible to have an LCD panel use one pixel clock rate, only to be > overridden by the HDMI transmitter's clock rate request when the second > display pipeline is enabled. > > This should be handled by having all the clock drivers honor clock rate > ranges, and have the consumers use clk_set_rate_min/clk_set_rate_max.
That, or relying on clk_set_rate_protect Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
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