From: Stephen Warren <[email protected]> This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate.
Signed-off-by: Stephen Warren <[email protected]> --- arch/arm/boot/dts/tegra-seaboard.dts | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index e188925..96516fb 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -281,7 +281,7 @@ }; i2c@7000c400 { - clock-frequency = <400000>; + clock-frequency = <100000>; }; i2c@7000c500 { -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
