[PATCH v6 11/25] clk: tegra: pll: Add code to handle if resets are supported by PLL

[Rhyland Klein]

From: Bill Huang <bilhu...@nvidia.com>

If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.

Reviewed-by: Benson Leung <ble...@chromium.org>
Signed-off-by: Bill Huang <bilhu...@nvidia.com>
Signed-off-by: Rhyland Klein <rkl...@nvidia.com>
---
v5:
  - Added kerneldoc for new members

v2:
  - Moved reset logic to _clk_pll_enable/disable as well

 drivers/clk/tegra/clk-pll.c |   12 ++++++++++++
 drivers/clk/tegra/clk.h     |    4 ++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 95ad0669291f..54ebab2b85e5 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw)
                udelay(2);
        }
 
+       if (pll->params->reset_reg) {
+               val = pll_readl(pll->params->reset_reg, pll);
+               val &= ~BIT(pll->params->reset_bit_idx);
+               pll_writel(val, pll->params->reset_reg, pll);
+       }
+
        clk_pll_enable_lock(pll);
 
        val = pll_readl_base(pll);
@@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw)
                writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
        }
 
+       if (pll->params->reset_reg) {
+               val = pll_readl(pll->params->reset_reg, pll);
+               val |= BIT(pll->params->reset_bit_idx);
+               pll_writel(val, pll->params->reset_reg, pll);
+       }
+
        if (pll->params->iddq_reg) {
                val = pll_readl(pll->params->iddq_reg, pll);
                val |= BIT(pll->params->iddq_bit_idx);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index dfbce9300547..b5131e4e4c75 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -176,6 +176,8 @@ struct div_nmp {
  * @lock_enable_bit_idx:       Bit index to enable PLL lock
  * @iddq_reg:                  PLL IDDQ register offset
  * @iddq_bit_idx:              Bit index to enable PLL IDDQ
+ * @reset_reg:                 Register offset of where RESET bit is
+ * @reset_bit_idx:             Shift of reset bit in reset_reg
  * @sdm_din_reg:               Register offset where SDM settings are
  * @sdm_din_mask:              Mask of SDM divider bits
  * @sdm_ctrl_reg:              Register offset where SDM enable is
@@ -239,6 +241,8 @@ struct tegra_clk_pll_params {
        u32             lock_enable_bit_idx;
        u32             iddq_reg;
        u32             iddq_bit_idx;
+       u32             reset_reg;
+       u32             reset_bit_idx;
        u32             sdm_din_reg;
        u32             sdm_din_mask;
        u32             sdm_ctrl_reg;
-- 
1.7.9.5

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