On Sun, 22 Apr 2001, Alan Cox wrote:

> > So my question was directed to what I've probably missed that ensures
> > cache synchronisation for DMA-mappings on x86.
> 
> Hardware. The x86 PC class machine is hardware cache coherent all the way.
> They also have strict in order store ordering and other nice properties - all
> at a cost.

Thanks for the clarification. I thought I read something about a
requirement to set PAGE_PCD for concurrent bus access in old i486 docs 
long time ago. Seems this was all obsoleted when Host-to-PCI bridges came
up to manage this. My expectation was, it might have gone just the other
direction with all these prefetch/posted write/delayed transaction
features.

Sorry for the noise!

Martin


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