The potential issue with using unaligned buffers is related to DMA-incoherent caches. If you have data laid out in memory like this:
// cache line starts here u8 cpu_writes_here_1 [size1]; u8 used_for_dma_read [dma_buflen]; u8 cpu_writes_here_2 [size2]; // cache line (maybe the Nth one) ends here
Then on certain kinds of system, there's no guarantee that the CPU writes won't get lost ... cpu writes to either the beginning or end of a cache line could get lost in certain cases, if the cache isn't properly flushed or that cache line is modified while the DMA is enabled.
Note that the issue comes up if "size1" is less than a cache line (makes it resemble a DMA alignment issue) as well as when "size2" is nonzero (doesn't look even vaguely like a DMA alignment issue).
Systems without such potential issues include x86 systems and most PPC ones.
This implies that on systems that do have this issue, kmalloc must not provide two different pieces of memory in the same cache line, since DMA done to one could wack the other.
No ... on those systems there are additional primitives that must be used, causing cache flushes. For the DMA mapping calls, flushing is done automatically. For "no mapping required" dma memory allocations, caching gets disabled.
So neither one is allowed to be cached, at least until the DMA finishes -- then it's a non-issue. Look at some of the arch code.
It does mean that on those systems, it's impossible to do memory allocation for potentially DMA-able memory without restricting allocations to cachline sizes. I think the slab code has long been known to have bugs in those areas. And a partial fix (2.5) recently got shot down, though for the wrong reason: because it was "wasting memory". The waste is not optional on those kinds of DMA-incoherent systems, though it is on x86 and some other systems.
Anyway, thanks for the explanation (as you can see, I finally managed to recover my lost email...),
:)
- Dave
Duncan.
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