> This doesn't sound like a particularly easy problem to solve. The
> simplest solution would be to copy unaligned data to a single large bounce
> buffer, thereby negating the advantages of direct I/O. Another
> possibility would be to have lots of little bounce buffers to take care of
> the "splices" -- the places where a maxpacket-sized transfer would have to
> span two adjacent s-g entries. That would involve less data movement but
> would require setting up twice as many URBs.
Two remarks.
1. Somebody supplying pathological buffers for direct IO gets the
performance he deserves
2. This isn't really the storage drivers problem. It should be solved
at a higher layer
So, if you need to do something in storage about it, choose the simple
solution and use a large bounce buffer.
> For the moment this isn't a very urgent problem, but it's something we
> should think about solving in the future. If anyone has any better ideas
> about how to fix it, I'd be pleased to hear them.
Secondly, I fear the analysis is incomplete.
On DMA incoherent machines, the size requirement is the transfer size
or a cacheline, whichever is larger and alignment needs to be on cacheline
boundaries.
Regards
Oliver
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