can happen even with a uniprocessor; the race relates to how the FIFO is managed for the OUT endpoint. Normally it's left ready to accept more data, so that firmware delays in decyphering the request won't slow down the typical case (no STALL). So the first data packet could have been ACKed even before the storage request has been interpreted.
Could/ should the device fill the OUT queue itself so that the hardware will NAK OUT til the firmware decides to ACK or STALL?
Curiously yours, Pat LaVarre
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