On Tue, Feb 08, 2005 at 10:26:51AM -0800, Matthew Dharm wrote:
On Tue, Feb 08, 2005 at 04:34:01PM +0100, Andi Kleen wrote:
So how does one use EHCI on an 8111, if the BIOS disables it anyway when needed? E.g., on an IBM IntelliStation A Pro Type 6224?
There's a bit somewhere in the southbridge (sorry would need
to look it up in the datasheet and you can do that as well yourself ;-)
Agreed, but then you did it, so thanks.
I'm looking at the July 2004 datasheet from AMD's web site now. I don't see this bit anywhere. I've also checked the errata list (April 2004) and there's nothing there, either.
Page 156 in version 3.0 of the Data sheet:
DevB:0x47: (Miscellaneous control register):Bit 7:When set the EHCI controller is disabled.
Just clear it.
DevB is the LPC bridge device, normally it has the PCI IDs Class 0604: 1022:7460
The version 3.0 8111 spec. says (p. 149): vendor:device default values are: 1022:7468, and that's what I see here (below).
Also the LPC Class is 0x060100 (or 0x0601 in first 16 bits; p. 150).
I wrote code to turn off the 0x80 bit at PCI config space offset 0x47 in DevB, or at least I think I did, but it's not working. Is it being done too late? The patch is attached.
Matt, did you try this? working for you?
-- ~Randy
/home/rddunlap$ lspci -xxx -s 0:7.0 00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 05) 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 14 10 b7 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 80 30 07 b1 01 00 00 02 2f 00 00 01 00 00 00 c0
linux-2611-rc3
Re-enable AMD 8111 southbridge EHCI controller if it is disabled.
Signed-off-by: Randy Dunlap <[EMAIL PROTECTED]>
diffstat:=
arch/i386/pci/common.c | 34 ++++++++++++++++++++++++++++++++++
drivers/pci/probe.c | 0
2 files changed, 34 insertions(+)
diff -Naurp ./arch/i386/pci/common.c~amd_ehci ./arch/i386/pci/common.c
--- ./arch/i386/pci/common.c~amd_ehci 2005-02-08 11:55:13.000000000 -0800
+++ ./arch/i386/pci/common.c 2005-02-08 17:10:14.000000000 -0800
@@ -13,6 +13,7 @@
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
+#include <asm/pci-direct.h>
#include "pci.h"
@@ -119,11 +120,44 @@ void __devinit pcibios_fixup_bus(struct
pci_read_bridge_bases(b);
}
+#ifdef CONFIG_X86_64
+void __devinit amd_ehci_reenable(int busnum)
+{
+ int dev, fn;
+
+ printk("PCI: reenable AMD EHCI: busnum=%d\n", busnum);
+
+ for (dev = 0; dev < 32; dev++)
+ for (fn = 0; fn < 8; fn++) {
+ u32 class, vend_dev;
+ class = read_pci_config(busnum, dev, fn,
+ PCI_CLASS_REVISION);
+ vend_dev = read_pci_config(busnum, dev, fn,
+ PCI_VENDOR_ID);
+ if ((class >> 8) == 0x060100 &&
+ ((vend_dev == (PCI_VENDOR_ID_AMD | 0x74600000)) ||
+ (vend_dev == (PCI_VENDOR_ID_AMD | 0x74680000)))) {
+ u32 misc = read_pci_config(busnum, dev, fn, 0x44);
+ printk("PCI: AMD LPC is found: dev=%#x, fn=%#x, misc=%#x\n",
+ dev, fn, misc);
+ if (misc & 0x80000000) { /* reg. 0x47 contains 0x80 bit */
+ misc &= ~0x80000000;
+ write_pci_config(busnum, dev, fn, 0x44, misc);
+ printk("PCI: enabled AMD EHCI\n");
+ }
+ }
+ }
+}
+#endif
struct pci_bus * __devinit pcibios_scan_root(int busnum)
{
struct pci_bus *bus = NULL;
+#ifdef CONFIG_X86_64
+ amd_ehci_reenable(busnum);
+#endif
+
while ((bus = pci_find_next_bus(bus)) != NULL) {
if (bus->number == busnum) {
/* Already scanned */
diff -Naurp ./drivers/pci/probe.c~amd_ehci ./drivers/pci/probe.c
