On Friday 22 April 2005 15.40, Lothar Wassmann wrote: > Probably you're right (though I wouldn't trust Intel > documentation farther than I can throw the PDF document ;), but > my scope was telling me that it worked as expected.
I see what you mean about the doc :-), especially true after a few days of training. > An SDRAM memory cycle may be 70ns, but UNCACHED_PHYS_0 is mapped > to phys addr 0x00000000 which is the static CS0 (usually FLASH > ROM) on PXA2xx. Of course, my mistake. I mixed things up with another CPU (SA-110?) where the flash was physically swapped with the SDRAM early in the boot process. Anyway, it still surprises me that you get a 700ns delay with only a single uncached read, even from flash memory, but never mind, it works. Robin ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_id=6595&alloc_id=14396&op=click _______________________________________________ [email protected] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
