Robin Farine writes: > Of course, my mistake. I mixed things up with another CPU (SA-110?) > where the flash was physically swapped with the SDRAM early in the > boot process. Anyway, it still surprises me that you get a 700ns > delay with only a single uncached read, even from flash memory, but > never mind, it works. > The main portion of the delay is probably accounted for by flushing and refilling the memory controllers pipeline. Thus the latency of the memory controller is the important factor, not the cycle time of an individual cycle.
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