On 02/02/2015 02:26 PM, Adrian Chadd wrote:
On 30 January 2015 at 18:06, Sujith Manoharan <suj...@msujith.org> wrote:
Peter Oh wrote:
Please refer the email thread that I mentioned about other architectures.
(dsb is for ARM and other platforms have the equivalent instruction such
as sfence, sync, mf, and dcs).
Ok.
Also the patch is updated with 2nd patch set replacing wmb to mb.
Would be good to test this on a MIPS platform...
The Atheros mips74k stuff I have here does /not/ flush all the writes
out to the device and guarantee the device has seen everything with a
memory barrier. Just saying. Various drivers ended up needing
ioread()s in my experiments; mips sync operations weren't enough.
So I'd suggest abstracting it out like the linux dri i915 code has -
they define a "posting read" macro which they use whenever they need
to ensure it's definitely made it all the way out to the hardware and
through internal FIFOs so internal hardware has seen the state change.
Then you can redefine that to your hearts content based on platform.
Thank you Adrian to head up the concern and suggestion.
The other people also concerned about other architectures like mips, so
I was going to analysis it.
But since you've already experienced the defects, let me hold the change
back until I find better for all.
-adrian
Regards,
Peter
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