From: "Teoh, Ji Sheng" <ji.sheng.t...@intel.com>
commit 2e242c460021e5a87b8caa567a9135b8f4cd764e from
https://github.com/altera-opensource/linux-socfpga.git
This patch updates the phy-mode of QSE device tree to 10gbase-r.
The reason for this change is, commit 7d6cd6c46cb7 ('net: eth: altera:
fix QSE driver broken link speed configuration') has updated PHY
interface from PHY_INTERFACE_MODE_10GKR to PHY_INTERFACE_MODE_10GBASER.
This fix will allow the QSE driver to initialize properly with the
correct PHY interface mode.
Signed-off-by: Teoh, Ji Sheng <ji.sheng.t...@intel.com>
Signed-off-by: Wenlin Kang <wenlin.k...@windriver.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
index ff4a9c194a82..c2a323832466 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse.dtsi
@@ -54,7 +54,7 @@ qse_0_qse: ethernet@0x100020000 {
<0x00000001 0x00000540 0x00000020>,
<0x00000001 0x00030100 0x00000010>;
dma-coherent;
- phy-mode = "10gbase-kr";
+ phy-mode = "10gbase-r";
sfp = <&sfp_eth0>;
clocks = <&ptp_ctrl_10G_clk>;
clock-names = "tod_clk";
--
2.25.1
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