From: Dinh Nguyen <dingu...@kernel.org>

commit e590fa8167f46629132bc0cc5576da7b9c0bc9c4 from
https://github.com/altera-opensource/linux-socfpga.git

[upstream commit 61cc507cd83b10bd561921d11386f524fcea419d]

The I2C pins on Intel's SoCFPGA platform are not connected to GPIOs and
thus cannot be recovered by the standard GPIO method. The driver has
been updated to use the "intel,socfpga-i2c" binding to reset the I2C
host for error recovery.

Link: https://lore.kernel.org/lkml/20220620230109.986298-1-dingu...@kernel.org/
Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
Signed-off-by: Wenlin Kang <wenlin.k...@windriver.com>
---
 arch/arm/boot/dts/socfpga.dtsi                    |  8 ++++----
 arch/arm/boot/dts/socfpga_arria10.dtsi            | 10 +++++-----
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 +++++-----
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi     | 10 +++++-----
 4 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 3e200b19b630..42ec73971d39 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -665,7 +665,7 @@ portc: gpio-controller@0 {
                i2c0: i2c@ffc04000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc04000 0x1000>;
                        resets = <&rst I2C0_RESET>;
                        clocks = <&l4_sp_clk>;
@@ -676,7 +676,7 @@ i2c0: i2c@ffc04000 {
                i2c1: i2c@ffc05000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc05000 0x1000>;
                        resets = <&rst I2C1_RESET>;
                        clocks = <&l4_sp_clk>;
@@ -687,7 +687,7 @@ i2c1: i2c@ffc05000 {
                i2c2: i2c@ffc06000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc06000 0x1000>;
                        resets = <&rst I2C2_RESET>;
                        clocks = <&l4_sp_clk>;
@@ -698,7 +698,7 @@ i2c2: i2c@ffc06000 {
                i2c3: i2c@ffc07000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc07000 0x1000>;
                        resets = <&rst I2C3_RESET>;
                        clocks = <&l4_sp_clk>;
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a5582e7a6afa..cc71f78175d1 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -552,7 +552,7 @@ fpga_mgr: fpga-mgr@ffd03000 {
                i2c0: i2c@ffc02200 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02200 0x100>;
                        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
@@ -563,7 +563,7 @@ i2c0: i2c@ffc02200 {
                i2c1: i2c@ffc02300 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02300 0x100>;
                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
@@ -574,7 +574,7 @@ i2c1: i2c@ffc02300 {
                i2c2: i2c@ffc02400 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02400 0x100>;
                        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
@@ -585,7 +585,7 @@ i2c2: i2c@ffc02400 {
                i2c3: i2c@ffc02500 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02500 0x100>;
                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
@@ -596,7 +596,7 @@ i2c3: i2c@ffc02500 {
                i2c4: i2c@ffc02600 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02600 0x100>;
                        interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 252f1937fb9d..88de32a8df3d 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -234,7 +234,7 @@ portb: gpio-controller@0 {
                i2c0: i2c@ffc02800 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02800 0x100>;
                        interrupts = <0 103 4>;
                        resets = <&rst I2C0_RESET>;
@@ -245,7 +245,7 @@ i2c0: i2c@ffc02800 {
                i2c1: i2c@ffc02900 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02900 0x100>;
                        interrupts = <0 104 4>;
                        resets = <&rst I2C1_RESET>;
@@ -256,8 +256,8 @@ i2c1: i2c@ffc02900 {
                i2c2: i2c@ffc02a00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
                        reg = <0xffc02a00 0x100>;
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        interrupts = <0 105 4>;
                        resets = <&rst I2C2_RESET>;
                        clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
@@ -267,7 +267,7 @@ i2c2: i2c@ffc02a00 {
                i2c3: i2c@ffc02b00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02b00 0x100>;
                        interrupts = <0 106 4>;
                        resets = <&rst I2C3_RESET>;
@@ -278,7 +278,7 @@ i2c3: i2c@ffc02b00 {
                i2c4: i2c@ffc02c00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02c00 0x100>;
                        interrupts = <0 107 4>;
                        resets = <&rst I2C4_RESET>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi 
b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index ee8b0555a0f5..1a4e9f6e35c8 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -233,7 +233,7 @@ portb: gpio-controller@0 {
                i2c0: i2c@ffc02800 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02800 0x100>;
                        interrupts = <0 103 4>;
                        resets = <&rst I2C0_RESET>;
@@ -244,7 +244,7 @@ i2c0: i2c@ffc02800 {
                i2c1: i2c@ffc02900 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02900 0x100>;
                        interrupts = <0 104 4>;
                        resets = <&rst I2C1_RESET>;
@@ -255,7 +255,7 @@ i2c1: i2c@ffc02900 {
                i2c2: i2c@ffc02a00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02a00 0x100>;
                        interrupts = <0 105 4>;
                        resets = <&rst I2C2_RESET>;
@@ -266,7 +266,7 @@ i2c2: i2c@ffc02a00 {
                i2c3: i2c@ffc02b00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02b00 0x100>;
                        interrupts = <0 106 4>;
                        resets = <&rst I2C3_RESET>;
@@ -277,7 +277,7 @@ i2c3: i2c@ffc02b00 {
                i2c4: i2c@ffc02c00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       compatible = "snps,designware-i2c";
+                       compatible = "intel,socfpga-i2c", "snps,designware-i2c";
                        reg = <0xffc02c00 0x100>;
                        interrupts = <0 107 4>;
                        resets = <&rst I2C4_RESET>;
-- 
2.25.1

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