From: John Jacques <[email protected]> By default, the simulator only support 4 cores; the normale device tree, axm55xxsim.dts, now matches. A 16 core dts is provided as well for the more adventurous.
Signed-off-by: John Jacques <[email protected]> --- arch/arm/boot/dts/axm55xxsim.dts | 96 -------- arch/arm/boot/dts/axm55xxsim16.dts | 459 ++++++++++++++++++++++++++++++++++++ 2 files changed, 459 insertions(+), 96 deletions(-) create mode 100644 arch/arm/boot/dts/axm55xxsim16.dts diff --git a/arch/arm/boot/dts/axm55xxsim.dts b/arch/arm/boot/dts/axm55xxsim.dts index 6e73be8..1c1cf0c 100644 --- a/arch/arm/boot/dts/axm55xxsim.dts +++ b/arch/arm/boot/dts/axm55xxsim.dts @@ -72,102 +72,6 @@ clock-frequency= <0>; cpu-release-addr = <0x10000020>; }; - - cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <4>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@5 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <5>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@6 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <6>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@7 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <7>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@8 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <8>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@9 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <9>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@10 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <10>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@11 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <11>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@12 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <12>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@13 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <13>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@14 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <14>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; - - cpu@15 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <15>; - clock-frequency= <0>; - cpu-release-addr = <0x10000020>; - }; }; clocks { diff --git a/arch/arm/boot/dts/axm55xxsim16.dts b/arch/arm/boot/dts/axm55xxsim16.dts new file mode 100644 index 0000000..6e73be8 --- /dev/null +++ b/arch/arm/boot/dts/axm55xxsim16.dts @@ -0,0 +1,459 @@ +/* + * arch/arm/boot/dts/axm55xxsim.dts + * + * Copyright (C) 2012 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/dts-v1/; + +/memreserve/ 0x00000000 0x00400000; + +/ { + model = "AXM5516"; + compatible = "arm", "lsi,axm5516-sim"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &axxia_serial0; + timer = &axxia_timers; + ethernet0 = &axxia_net0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <4>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <5>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <6>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <7>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@8 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <8>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@9 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <9>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@10 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <10>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@11 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <11>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@12 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <12>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@13 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <13>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@14 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <14>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + + cpu@15 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <15>; + clock-frequency= <0>; + cpu-release-addr = <0x10000020>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + cpu { + frequency = <1400000000>; + }; + + peripheral { + frequency = <400000000>; + }; + + emmc { + frequency = <25000000>; + }; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; + }; + + gic: interrupt-controller@2001001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x20 0x01001000 0 0x1000>, /* gic dist base */ + <0x20 0x01002000 0 0x100>, /* gic cpu base */ + <0x20 0x01004000 0 0x2000>, /* vgic control */ + <0x20 0x01006000 0 0x2000>, /* vgic cpu base */ + <0x20 0x10030000 0 0x100>, /* axm IPI mask reg base */ + <0x20 0x10040000 0 0x20000>; /* axm IPI send reg base */ + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + + gpdma@2020140000 { + compatible = "lsi,dma32"; + reg = <0x20 0x20140000 0x00 0x1000>; + interrupts = <0 60 4>, /* busy */ + <0 61 4>; /* error */ + + channel0 { + interrupts = <0 62 4>; + }; + + channel1 { + interrupts = <0 63 4>; + }; + }; + + gpdma@2020141000 { + compatible = "lsi,dma32"; + reg = <0x20 0x20141000 0x00 0x1000>; + interrupts = <0 64 4>, /* busy */ + <0 65 4>; /* error */ + + channel0 { + interrupts = <0 66 4>; + }; + + channel1 { + interrupts = <0 67 4>; + }; + }; + + gpreg@2010094000 { + compatible = "lsi,gpreg"; + reg = <0x20 0x10094000 0 0x1000>; + }; + + mtc@2010098000 { + compatible = "lsi,mtc"; + reg = <0x20 0x10098000 0 0x3000>; + interrupts = <0 45 4>; + }; + + axxia_net0: ethernet@201100000000 { + compatible = "smsc,lan91c111"; + device_type = "network"; + reg = <0x20 0x11000000 0 0x10000>; + interrupts = <0 1 4>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mmci@020101E0000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x20 0x101E0000 0x00 0x1000>; + interrupts = <0 222 4>, + <0 223 4>; + }; + + axxia_serial0: uart@2010080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10080000 0x00 0x1000>; + interrupts = <0 56 4>; + }; + + axxia_serial1: uart@2010081000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10081000 0x00 0x1000>; + interrupts = <0 57 4>; + }; + + axxia_serial2: uart@2010082000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10082000 0x00 0x1000>; + interrupts = <0 58 4>; + }; + + axxia_serial3: uart@2010083000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10083000 0x00 0x1000>; + interrupts = <0 59 4>; + }; + + axxia_timers: timer@2010091000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x20 0x10091000 0 0x1000>; + interrupts = <0 46 4>, + <0 47 4>, + <0 48 4>, + <0 49 4>, + <0 50 4>, + <0 51 4>, + <0 52 4>, + <0 53 4>; + }; + + gpio@2010092000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20 0x10092000 0 0x1000>; + interrupts = <0 10 4>, + <0 11 4>, + <0 12 4>, + <0 13 4>, + <0 14 4>, + <0 15 4>, + <0 16 4>, + <0 17 4>; + }; + + gpio@2010093000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20 0x10093000 0x00 0x1000>; + interrupts = <0 18 4>; + }; + + ssp@2010088000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x20 0x10088000 0x00 0x1000>; + interrupts = <0 42 4>; + }; + + }; + + PCIE0: pciex@0x3000000000 { + compatible = "lsi,plb-pciex"; + device_type = "pci"; + status = "ok"; + port = <0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + /* config space access MPAGE7 registers*/ + reg = < 0x30 0x38000000 0x0 0x01000000 + 0x20 0x20120000 0x0 0x00008000 >; + /* Outbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >*/ + ranges = <0x03000000 0x00000000 0xa0000000 + 0x30 0x00000000 + 0x00 0x20000000>; + /* Inbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ + dma-ranges = <0x03000000 0x00000000 0x00000000 + 0x00 0x00000000 + 0x00 0x40000000>; + interrupts = <0 68 4>, + <0 73 4>, + <0 74 4>, + <0 75 4>, + <0 76 4>, + <0 77 4>, + <0 78 4>, + <0 79 4>, + <0 80 4>, + <0 81 4>, + <0 82 4>, + <0 83 4>, + <0 84 4>, + <0 85 4>, + <0 86 4>, + <0 87 4>, + <0 88 4>; + }; + + PCIE1: pciex@0x3080000000 { + compatible = "lsi,plb-pciex"; + device_type = "pci"; + status = "ok"; + port = <1>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + /* config space access MPAGE7 registers*/ + reg = <0x30 0xb8000000 0x0 0x01000000 + 0x20 0x20130000 0x0 0x00008000 >; + /* Outbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ + ranges = <0x03000000 0x00000000 0xa0000000 + 0x30 0x80000000 + 0x00 0x20000000>; + /* Inbound ranges */ + /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ + dma-ranges = <0x03000000 0x00000000 0x00000000 + 0x00 0x00000000 + 0x00 0x40000000>; + interrupts = <0 70 4>; + }; + + I2C0: i2c@0x02010084000 { + compatible = "lsi,api2c"; + device_type = "i2c"; + enabled = <0>; + port = <0>; + /* bus_name = "auto"; */ + /* bus = <2>; */ + reg = <0x20 0x10084000 0x00 0x1000>; + interrupts = <0 19 4>; + }; + + I2C1: i2c@0x02010085000 { + compatible = "lsi,api2c"; + device_type = "i2c"; + enabled = <0>; + port = <1>; + /* bus_name = "auto"; */ + /* bus = <3>; */ + reg = <0x20 0x10085000 0x00 0x1000>; + interrupts = <0 20 4>; + }; + + I2C2: i2c@0x02010086000 { + compatible = "lsi,api2c"; + device_type = "i2c"; + enabled = <0>; + port = <2>; + /* bus_name = "auto"; */ + /* bus = <4>; */ + reg = <0x20 0x10086000 0x00 0x1000>; + interrupts = <0 21 4>; + }; + + SMB: i2c@0x02010087000 { + compatible = "lsi,api2c"; + device_type = "i2c"; + enabled = <0>; + port = <3>; + bus_name = "smb"; + /* bus = <5>; */ + reg = <0x20 0x10087000 0x00 0x1000>; + interrupts = <0 22 4>; + }; +}; + +/* + Local Variables: + mode: C + End: +*/ -- 1.7.9.5 _______________________________________________ linux-yocto mailing list [email protected] https://lists.yoctoproject.org/listinfo/linux-yocto
