On 14-01-20 12:56 PM, Charlie Paul wrote:
From: SangeethaRao <[email protected]>
Updated PCIe driver to set PCIe BASE_ADDR1 register to 0x0 without
which PCIe inbound access wasn't working and we were seeing several
suprious PEI interrupts including BAR mismatch interrupt.
Signed-off-by: SangeethaRao <[email protected]>
Signed-off-by: Paul Butler <[email protected]>
---
arch/arm/mach-axxia/pci.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-axxia/pci.c b/arch/arm/mach-axxia/pci.c
index c0c030f..1a5cebf 100644
--- a/arch/arm/mach-axxia/pci.c
+++ b/arch/arm/mach-axxia/pci.c
@@ -311,8 +311,7 @@ arm_pciex_axxia_read_config(struct pci_bus *bus,
}
#ifdef PRINT_CONFIG_ACCESSES
- pr_info("acp_read_config for PCIE%d: %3d fn=0x%04x o=0x%04x l=%d "
- "a=0x%08x v=0x%08x, dev=%d\n",
+ pr_info("acp_read_config for PCIE%d: %3d fn=0x%04x o=0x%04x l=%d a=0x%08x
v=0x%08x, dev=%d\n",
port->index, bus->number, devfn, offset, len,
bus_addr, *val, PCI_SLOT(devfn));
This commit has another mix of cleanups and functional changes,
and should be two patches.
Bruce
#endif
@@ -376,8 +375,7 @@ arm_pciex_axxia_write_config(struct pci_bus *bus,
}
#ifdef PRINT_CONFIG_ACCESSES
- pr_info("acp_write_config: bus=%3d devfn=0x%04x offset=0x%04x len=%d"
- "addr=0x%08x val=0x%08x\n",
+ pr_info("acp_write_config: bus=%3d devfn=0x%04x offset=0x%04x len=%d
addr=0x%08x val=0x%08x\n",
bus->number, devfn, offset, len, bus_addr, val);
#endif
@@ -663,20 +661,24 @@ static int axxia_pcie_setup(int portno, struct
pci_sys_data *sys)
/* Configure the inbound window size */
inbound_size = (u32) resource_size(&port->inbound);
- writel(inbound_size, port->regs + PCIE_RC_BAR0_SIZE);
+ writel(~(inbound_size-1), port->regs + PCIE_RC_BAR0_SIZE);
/* Verify BAR0 size */
{
u32 bar0_size;
writel(~0, port->regs + PCI_BASE_ADDRESS_0);
bar0_size = readl(port->regs + PCI_BASE_ADDRESS_0);
- if ((bar0_size & ~0xf) != inbound_size)
+ if ((bar0_size & ~0xf) != ~(inbound_size-1))
pr_err("PCIE%d: Config BAR0 failed\n", port->index);
}
/* Set the BASE0 address to start of PCIe base */
writel(port->pci_bar, port->regs + PCI_BASE_ADDRESS_0);
+ /* Set the BASE1 address to 0x0 */
+ writel(0x0, port->regs + PCI_BASE_ADDRESS_1);
+
+
/* Setup TPAGE registers for inbound mapping
*
* We set the MSB of each TPAGE to select 128-bit AXI access. For the
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