On 2015-01-12 5:41 AM, Abhishek Paliwal wrote:
These patches cover basic OCTEONIII support.
Hi Abhishek, The changes all look sane to me (in particular the upstream backports are easy to integrate). But the big question is .. what linux-yocto variant is this for ? We have a few choices: 3.10, 3.14 or 3.17 at the moment. I could figure it out by seeing where your upstream commits land in the kernel history, but I'd rather ask and see your response. And finally, can you elaborate on a particular OcteonIII board that is known to work with this series applied ? Bruce
Abhishek Paliwal (9): MIPS OCTEON Add OCTEON3 to get cpu type MIPS OCTEON Enable use of FPU MIPS Add function get ebase cpunum MIPS Add minimal support for OCTEON3 to c-r4k.c MIPS donot build fast TLB refill handler with 32-bit kernels. MIPS Override assembler ISA for kernel FPU instruction. MIPS: Octeon: Implement the core-16057 workaround MIPS: Octeon: CVMSEG LM loads may cause dcache parity errors MIPS:OCTEON: More OCTEONIII support arch/mips/Makefile | 7 + arch/mips/cavium-octeon/csrc-octeon.c | 7 + arch/mips/cavium-octeon/setup.c | 12 +- arch/mips/include/asm/cpu-type.h | 1 + .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 - .../asm/mach-cavium-octeon/kernel-entry-init.h | 43 +- arch/mips/include/asm/mipsregs.h | 8 + arch/mips/include/asm/octeon/cvmx-rst-defs.h | 564 +++++++++++++++++++++ arch/mips/include/asm/r4kcache.h | 2 + arch/mips/kernel/Makefile | 2 +- arch/mips/kernel/branch.c | 6 +- arch/mips/kernel/cpu-probe.c | 2 +- arch/mips/kernel/octeon_switch.S | 85 +++- arch/mips/kernel/ptrace.c | 24 +- arch/mips/kernel/ptrace32.c | 12 +- arch/mips/kernel/r4k_switch.S | 3 + arch/mips/math-emu/cp1emu.c | 12 +- arch/mips/mm/c-r4k.c | 47 +- arch/mips/mm/tlbex.c | 8 +- 19 files changed, 798 insertions(+), 48 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-rst-defs.h -- 1.8.1.4 "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
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