From: Abhishek Paliwal <abhishek.pali...@aricent.com>
From: David Daney <david.da...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Abhishek Paliwal <abhishek.pali...@aricent.com>
---
arch/mips/cavium-octeon/setup.c | 4 +---
.../include/asm/mach-cavium-octeon/kernel-entry-init.h | 18 ++++++++++++++++--
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 270cb3c..eccf9a9 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -580,12 +580,10 @@ void octeon_user_io_init(void)
/* R/W If set, CVMSEG is available for loads/stores in user
* mode. */
cvmmemctl.s.cvmsegenau = 0;
- /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
- * is max legal value. */
- cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
write_c0_cvmmemctl(cvmmemctl.u64);
+ /* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 0030c80..f5ab254 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -9,10 +9,10 @@
#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
-#define CP0_CYCLE_COUNTER $9, 6
#define CP0_CVMCTL_REG $9, 7
#define CP0_CVMMEMCTL_REG $11,7
#define CP0_PRID_REG $15, 0
+#define CP0_DCACHE_ERR_REG $27, 1
#define CP0_PRID_OCTEON_PASS1 0x000d0000
#define CP0_PRID_OCTEON_CN30XX 0x000d0200
@@ -60,7 +60,7 @@
skip:
# First clear off CvmCtl[IPPCI] bit and move the performance
# counters interrupt to IRQ 6
- li v1, ~(7 << 7)
+ dli v1, ~(7 << 7)
and v0, v0, v1
ori v0, v0, (6 << 7)
@@ -90,6 +90,20 @@ skip:
sync
# Flush dcache after config change
cache 9, 0($0)
+ # Zero all of CVMSEG to make sure parity is correct
+ dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+ dsll v0, 7
+ beqz v0, 2f
+1 : dsubu v0, 8
+ sd $0, -32768(v0)
+ bnez v0, 1b
+2 :
+ mfc0 v0, CP0_PRID_REG
+ bbit0 v0, 15, 1f
+ # OCTEON II or better have bit 15 set. Clear the error bits.
+ dli v0, 0x27
+ dmtc0 v0, CP0_DCACHE_ERR_REG
+1 :
# Get my core id
rdhwr v0, $0
# Jump the master to kernel_entry
--
1.8.1.4
--
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