From: Abhishek Paliwal <abhishek.pali...@aricent.com>
From: Chandrakala Chavva <ccha...@caviumnetworks.com>
Fix reading LMCX_DLL_CTL2 CSR fields.
Read LMCX_DLL_CTL2<quad_dll_ena> from the correct struct.
Fix RML_TO error in octeon-lmc.
Use correct CSR for disabling ECC errors interrupts for Octeon II.
Register octeon-lmc only if DDR controller is present.
Check for LMCX_DLL_CTL2[QUAD_DLL_ENA]
which is set correctly for all OcteonII models.
Signed-off-by: Chandrakala Chavva <ccha...@caviumnetworks.com>
Signed-off-by: Leonid Rosenboim <lrosenb...@caviumnetworks.com>
Signed-off-by: Abhishek Paliwal <abhishek.pali...@aricent.com>
---
arch/mips/cavium-octeon/dma-octeon.c | 5 +++--
arch/mips/cavium-octeon/octeon-platform.c | 1 +
arch/mips/cavium-octeon/setup.c | 6 +++++-
arch/mips/include/asm/octeon/octeon.h | 14 +++++++++++++-
drivers/edac/octeon_edac-lmc.c | 16 +++++++++++++---
drivers/edac/octeon_edac-pc.c | 2 +-
6 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/arch/mips/cavium-octeon/dma-octeon.c
b/arch/mips/cavium-octeon/dma-octeon.c
index 02f2444..92513be 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -276,7 +276,8 @@ void __init plat_swiotlb_setup(void)
continue;
/* These addresses map low for PCI. */
- if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (e->addr > 0x410000000ull &&
+ current_cpu_type() != CPU_CAVIUM_OCTEON2)
continue;
addr_size += e->size;
@@ -308,7 +309,7 @@ void __init plat_swiotlb_setup(void)
#endif
#ifdef CONFIG_USB_OCTEON_OHCI
/* OCTEON II ohci is only 32-bit. */
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
+ if (current_cpu_type() == CPU_CAVIUM_OCTEON2 && max_addr >=
0x100000000ul)
swiotlbsize = 64 * (1<<20);
#endif
swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
diff --git a/arch/mips/cavium-octeon/octeon-platform.c
b/arch/mips/cavium-octeon/octeon-platform.c
index 6df0f4d..285238b 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -687,6 +687,7 @@ end_led:
alias_prop = fdt_getprop(initial_boot_params, aliases,
"usbn", NULL);
if (alias_prop) {
+
int usbn = fdt_path_offset(initial_boot_params, alias_prop);
if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d65238d..fc0b0d2 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -393,7 +393,7 @@ void octeon_check_cpu_bist(void)
pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
coreid, bist_val);
- write_octeon_c0_dcacheerr(0);
+ write_octeon_c0_dcacheerr(0);
}
/**
@@ -582,6 +582,10 @@ void octeon_user_io_init(void)
* mode. */
cvmmemctl.s.cvmsegenau = 0;
+ /* Enable TLB parity error reporting on OCTEON II */
+ if (current_cpu_type() == CPU_CAVIUM_OCTEON2)
+ cvmmemctl.s.tlbperrena = 1;
+
write_c0_cvmmemctl(cvmmemctl.u64);
/* Setup of CVMSEG is done in kernel-entry-init.h */
diff --git a/arch/mips/include/asm/octeon/octeon.h
b/arch/mips/include/asm/octeon/octeon.h
index f5d77b9..c809f86 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -127,7 +127,19 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
uint64_t wbfbist:1;
/* Reserved */
- uint64_t reserved:22;
+ uint64_t reserved:13;
+ /* When set, TLB parity errors can occur. */
+ uint64_t tlbperrena:1;
+ /* OCTEON II - When set, CVMSET LM parity errors are enabled. */
+ uint64_t lmemperrena:1;
+ /* OCTEON II - If set, NUDGE/WRITEBACK_INVALIDATE,
+ * NUDGE_WB, EVICT_SOON, LC, CONT_WRITE_BACK,
+ * PREPARE_FOR_STORE and PREPARE_FOR_STORE_THROUGH
+ * prefetch operations become NOPs. */
+ uint64_t disstpref:1;
+ /* OCTEON II - If set, NORMAL and NOTL2 prefetch
+ * operations become NOPs. */
+ uint64_t disldpref:1;
/* R/W If set, marked write-buffer entries time out
* the same as as other entries; if clear, marked
* write-buffer entries use the maximum timeout. */
diff --git a/drivers/edac/octeon_edac-lmc.c b/drivers/edac/octeon_edac-lmc.c
index 93412d6..0c9b497 100644
--- a/drivers/edac/octeon_edac-lmc.c
+++ b/drivers/edac/octeon_edac-lmc.c
@@ -130,8 +130,18 @@ static int octeon_lmc_edac_probe(struct platform_device
*pdev)
/* OCTEON II */
union cvmx_lmcx_int_en en;
union cvmx_lmcx_config config;
+ union cvmx_lmcx_dll_ctl2 ctl2;
+
+ /* Check if LMC controller is enabled. */
+ ctl2.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(mc));
+ if ((current_cpu_type() == CPU_CAVIUM_OCTEON3 &&
ctl2.cn70xx.quad_dll_ena == 0)
+ || (current_cpu_type() == CPU_CAVIUM_OCTEON2
+ && ctl2.cn63xx.quad_dll_ena == 0)) {
+ dev_info(&pdev->dev, "Disabled (LMC not present)\n");
+ return 0;
+ }
- config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));
+ config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(mc));
if (!config.s.ecc_ena) {
dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
return 0;
@@ -154,10 +164,10 @@ static int octeon_lmc_edac_probe(struct platform_device
*pdev)
return -ENXIO;
}
- en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
+ en.u64 = cvmx_read_csr(CVMX_LMCX_INT_EN(mc));
en.s.intr_ded_ena = 0; /* We poll */
en.s.intr_sec_ena = 0;
- cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);
+ cvmx_write_csr(CVMX_LMCX_INT_EN(mc), en.u64);
}
platform_set_drvdata(pdev, mci);
diff --git a/drivers/edac/octeon_edac-pc.c b/drivers/edac/octeon_edac-pc.c
index 0f83c33..380cbe2 100644
--- a/drivers/edac/octeon_edac-pc.c
+++ b/drivers/edac/octeon_edac-pc.c
@@ -73,7 +73,7 @@ static int co_cache_error_event(struct notifier_block *this,
edac_device_handle_ce(p->ed, cpu, 0, "dcache");
/* Clear the error indication */
- if (OCTEON_IS_MODEL(OCTEON_FAM_2))
+ if (current_cpu_type() == CPU_CAVIUM_OCTEON2)
write_octeon_c0_dcacheerr(1);
else
write_octeon_c0_dcacheerr(0);
--
1.8.1.4
--
_______________________________________________
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto
