"Eric W. Biederman" wrote:
>
> Ollie Lho and I have worked together and we have tracked down what in
> the K7 initialization is needed to get good resonable memory
> performance. And it is not L2 cache initialization.
>
This seems to be "implied" by the AMD Porcessor Recognition App Note.
It says only K7 CPUs of Model 1 and 2 need to init L2 cache.
Model 1,2 are slot Athlon. Socket Atholon is Model 4 and Duron is
Model 3.
This has been explained by Bari in a private mail. (but I was too
stupid to know what he was talking about at that time).
Ollie
